Turn-around time is typically 24 hours to 2 weeks, depending on complexity of design.

Technology

1. The red stars (*) indicate required fields.

2. Foundry: * IBM generic TSMC SMIC UMC Global Foundries Tower XFab Austria Mycrosystems Other (Request)
3. Process: * 32nm 45nm 65nm 90nm 130nm 180nm 250nm 330nm
4. Flavor:
5. No. of Thin Layers: * 3 4 5 6 7 8 9 10
6. No. of Thick Layers: * 1 2 3 4
7. No. of Ultra Thick Layers: * 1 2 3 4

Global Preferences

1. These settings are applicable globally, regardless of block/sub-circuit type.

2. Power Nets: *
3. Ground Nets: *

I/O Preferences

1. Use bump pads: No Yes
2. Library:
3. Cell:

Circuit Specification

1. Top-level design specification.

2. Category: ADC DAC PLL Amplifier VCO Mixer PD+Charge Pump
Type: Choose one
3. Differential: No Yes
4. Optimize: No Yes
5. INPUTS
6. Supply Min/Max : /
7. Temperature Min/Max: / (degrees Celsius)
8. Model Section Typ:
9. Model Section Slow:
10. Model Section Fast:
11. Signal Input Min/Max: / (volts)
12. Signal Input Rise/Fall Time: (seconds)
13. Load Capacitance to Ground: (farads)
14. OUTPUTS

Measurement Name	Target	Cost

Digital Preferences

1. These settings are only relevant to blocks specified as "digital".

2. RMS Current: (amperes)
3. Clock Frequency: (hertz)
4. Clock Rise-Time: (seconds)
5. Latch Cell:
6. Latch Clock Pin:
7. Latch D Pin:
8. Latch Q Pin:
9. Latch Qb Pin:

Supporting Files

1. Files that pertain to this design.

2. Netlist: *
3. OR
4. Standard Cell Library: *

Contact Information

1. We will need to call or e-mail you to discuss this project.

2. Contact Name: *
3. Company Name: *
4. E-mail: *
5. Confirm E-mail: *
6. Office Phone: * Ext:
7. Cell Phone:

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