Frequently Asked Questions

Here are a few common questions we get asked about Analog Rails. Perhaps this will answer a few of yours...

  • Q: What is Analog Rails?
  • A: Analog Rails is a complete AUTOMATED MIXED-SIGNAL EDA platform that allows the senior circuit designer to be a "One Stop Shop". NO CAD NOR LAYOUT DESIGNERS NEEDED. Even design management into all popular revision control systems is included. It combines automation (front to back), correct by construction manual editing, and verification that allows mixed signal designs to be designed from scratch or migrated in minutes rather than months. We are native on Open Access database.

  • Q: Didn't you know that you cannot automate analog?
  • A: We did not know that, so we did it.

  • Q: I never heard of Analog Rails. Are you a startup company?
  • A: No. We are an upstart company.

  • Q: Is Analog/Digital Rails available outside of the US
  • A: It is also available in Canada, but I don't know why.

  • Q: Can our layout designers use Analog Rails?
  • A: No. Circuit designers should do their own layouts. Automation of layout structures and routes allow simulation with all parasitics at all times. The circuit designers create better layouts by utilizing black space and making tradeoffs that the layout designer cannot make. Automation enables "what if" scenarios. Our automatic router is DRC/LVS correct and ELECTRICALLY AWARE. The layout designer has no chance against our automation coupled with the circuit designer.

  • Q: Can our junior engineers use Analog Rails?
  • A: Nah. This is automation. Get rid of them too.

  • Q: Can we run the licenses from home due to the coronavirus?
  • A: Since every engineer will be 10x more productive, engineers can now sit 60 feet apart. Go back to work!

  • Q: How much CAD support is needed?
  • A: None. Analog Rails is a complete flow that includes design/data management and PDKs. If you find a process that we don't handle, we can get it done in a week. The PDK configurations are text files, so the customer can easily modify them. The data management system works with SVN (open source), but you can utilize commercial systems if you want to waste your money.

  • Q: I noticed you have digital place and route? I thought you just had analog automation.

  • A: We expanded. Run digital place and route with a touch of a button, all within the Analog Rails design environment. Just like in analog mode, full cross probing and synchronization with the schematic is maintained. We have our own built-in standard cell library with liberty and verilog files. We also have our own static timing tools that includes RCx to unit time delays for all datapaths.

  • Q: How accurate are your pcell's parasitics?

  • A: Far more accurate than the 25 year old tool that you are currently using. The proper STI layout effects will be netlisted out AT ALL TIMES based on abutment, well distances, diffusion group distances, etc. Our schematic and layout are synchronized. We know that the real values are.

  • Q: How do you set matching?

  • A: Press "=" and the pair of devices to interdigitize. Simple. These common centroid differential structures with a symmetrical guard ring and gate protection diodes are automatically generated. The differential router creates a shielded wall.

  • Q: How do we customize?

  • A: Hearing the complaints that Analog Rails has taken the “creativity away from the analog circuit designer”, advanced customization features have been added for engineers who get paid by the hour, or the religious engineer who really believes that only they have mastered true symmetry.

  • Q: How do you handle high speed signals?

  • A: Tag nets as "RF", to leave plenty of space in the route. We minimize Cdg (miller capacitance) and Cds with optimizers

  • Q: How do you see electromigration (EM) and IR drop?

  • A: For EM: User selects "%". All route segments and vias exceeding that show up in layout. For R, I, and V: Just select 2 points in the layout.

  • Q: Is there an "ECO" mode? Can we decouple the layout?

  • A: Yes and Yes. The user can synchronize, unsynchronize, and even put the layout in "derailed" mode. The user can also make manual modifications after the router completes, then can optionally rerun that router to finish uncompleted routes. We are always LVS aware.

  • Q: Why do we need layout on the fly?

  • A: For simulation accuracy. At feature sizes below 130n, SA and SB have a large effect. The bogus pre-layout calculations that are provided in cdf callbacks are no longer going to cut it. There is no reason for the circuit designer to wait several days/weeks for the layout to get done to get the parasitics.

  • Q: Can you handle finfet (16n / 14n) and other new processes?

  • A: Yes. Customers taped out on both.

  • Q: You expect me to believe this is really "correct by construction?"

  • A: http://www.correctbyconstruction.com... see?

  • Q: How about manual routing?

  • A: Very powerful. Connectivity and DRC rule aware, collision avoidance, automatic maximum via insertion. Terminals light up during routing to show possible end points. Thicken wires a pitch at a time with a mouse click. More powerful than Virtuoso.

  • Q: And the automatic router?

  • A: Correct by Construction™. DRC/LVS correct. Minimizes capacitance. User setable RF, differential, shielded nets, power mesh, differential and signal aware density fill, automatic well tap connection, automatic gate protection diodes and antenna rules, double via option. Differential routes shielded. Single-ended shielded routing option (set in schematic). Maximum wire length and area per layer. We currently handle the new design rules down to 14nm

  • Q: Is your optimizer difficult to use?

  • A: Not ours. The simulation environment was built with the optimizer in mind. Place the predefined or custom measurements into the schematic, use our testbench templates or build your own, then launch. Optimizer over all corners and all analysis at the same time. We have 2 global and 2 local optimizers. User can force minimum Vds-Vdsat, Vod, etc.

  • Q: Can we just buy the pieces we need?

  • A: No. The flow stays together, which consists of schematic, simulation environment, simulators (unlimited), optimizer, layout, placers, routers (single ended, RF, differential, power mesh, digital), parasitic extractor, migrator, mimic layout, compactor, nudger, design/data management, and PDK GUI. They play nicely together. The whole is worth more than the sum of the parts. Why separate them? Keep in mind, we are native to OA. By definition, you can use 3rd party tools with our output (open the design in Virtuoso, run calibre, hspice, etc)

  • Q: We successfully use Cadence Virtuoso to make chips. Why do we need Analog Rails?

  • A: Grandma successfully used a washing board... then the washing machine came out. Get your chip out 10x faster, while keeping your IP safe at home. No need to outsource. What will happen to your company when your competitors go with automation?

  • Q: Are you complimentary to Virtuoso?

  • A: We read/write based on the same database (Open Access), so you can use both platforms at the same time. We also produce extracted views to allow the user to verify from anywhere. Then again, we don't see a reason to stick with your archaic flow. Analog Rails can replace Virtuoso + all of your surrounding infrastructure.

  • Q: We trust Cadence. After all, didn't they invent the electron?

  • A: No. The electron existed several years before Cadence was formed, so they were unable to patent it. As far as trusting Cadence, most of you don't. Most companies use Mentor's Calibre for DRC & LVS. There are a ton of foundry approved simulators. We support most simulators

  • Q: Analog Rails? What's with the "Rails?"

  • A: Initially, we used "Analog on Rails", but we dropped the "on". The "Rails" represents a framework to create integrated circuits quickly. No steering needed. We know the direction you want to go in.

  • Q: Is Analog Rails cheaper than VXL?

  • A: No. A bulldozer is more expensive than a shovel.

  • Q: What cheap labor area do you export your work to?

  • A: We off-loaded work from Scottsdale to Tempe to take advantage of the cheaper labor rates.

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